1. Field of the Invention
This application relates generally to electronic test equipment and more specifically to equipment for testing populated printed circuit boards for manufacturing defects.
2. Description of the Prior Art
During the manufacture and subsequent handling of printed circuit boards, defects such as unwanted open circuits or short circuits may develop in or between circuit pathways and electronic components. It is necessary to perform automated testing of printed circuit boards both for manufacturing quality control and for maintenance purposes.
Testing printed circuit boards is becoming increasingly difficult and more expensive as the use of surface mount technology increases and as integrated circuits and printed circuit boards become more complex and operate at higher frequencies. Conventional techniques for automated printed circuit board testing involve applying signals through a set of test pins and measuring output signals on other test pins. "Functional testing" can be performed by energizing the printed circuit board, applying a preselected set of input signals, and determining whether the proper output signals are generated by the circuitry on the board being tested. Alternatively, a printed circuit board may be tested on a "bed-of-nails" tester that comprises pins which contact the metallic traces on the printed circuit board being tested so that selected input signals may be applied at various nodes on the printed circuit board, and corresponding output signals can be measured at other nodes on the printed circuit board. Conventional bed-of-nails testing requires that the functionality of the circuits mounted on the board under test be known, so that test routines can be written to isolate the circuitry of interest, to apply input signals to the appropriate nodes, and to generate expected output signals to be received from other nodes.
One alternative printed circuit board testing method is described in U.S. Pat. No. 5,218,294, issued Jun. 8, 1993 to Soiferman. The Soiferman patent disclosed stimulating a printed circuit board through the power and ground lines of the board with an AC signal and then contactlessly measuring the electromagnetic near field distribution proximate the board being tested. The electromagnetic "signature" of the board being tested was compared to the electromagnetic signature of a known good circuit board to determine whether the board under test was defective.
Another approach to printed circuit board testing is disclosed in U.S. Pat. No. 5,124,660, issued on Jun. 23, 1992 to Cilingiroglu. That patent disclosed a system to determine whether input and output leads of a semiconductor component are properly connected to a printed circuit board. The system includes an oscillator which is connected to a metallic electrode placed on top of an integrated circuit package that is mounted on a printed circuit board. A probe pin of a bed-of-nails tester is connected to a current measuring device, and the pin is also connected to a printed circuit board wiring trace that is supposed to be soldered to the component lead being tested. An oscillator signal is capacitively coupled from the metallic electrode on top of the integrated circuit package through the integrated circuit package to the lead being tested. If the lead being tested is properly connected to the printed circuit board, current can be measured in the appropriate trace on the printed circuit board.
The approach described in the Cilingiroglu patent has several deficiencies. First, it can miss hairline fractures in components or in connections because the test signal may capacitively couple across small, but incapacitating, gaps between conductors. Second, it only tests the connection between the pin of a component and the PC board traces, and it does not test any of the intra-component connections, such as between the integrated circuit itself and the pin that extends from the package, which may be caused by a missing or defective bond wire connection. Third, it only tests whether any pin of the component is connected to a node on the PC board, and it does not give any indication of whether the component is properly inserted into the PC board with the correct orientation. Finally, because this approach relies on capacitive coupling between the lead frame of the integrated circuit and the metallic electrode, the presence of a ground plane or a metal heat sink within or above the integrated circuit can prevent reliable results from being obtained.
U.S. Pat. No. 5,254,953 to Crook et al. is owned by the same assignee and similarly relates to a technique for detecting opens using capacitive coupling. In Crook's patent, a signal is introduced to a pin under test through a probe contacting a trace on the printed circuit board. A conductive electrode is placed over the component being tested and connected to a current measuring device. If the part is properly connected to the printed circuit board, the signal is capacitively coupled to the current measuring device. Detection of the coupled signal indicates a good connection between the pin and the printed circuit board.
U.S. Pat. No. 4,829,238, issued May 9, 1989 to Goulette, et al., discloses monitoring electromagnetic emissions from a printed circuit board by energizing the board while it is located adjacent an array of electromagnetic emission measuring probes. A division from that application, U.S. Pat. No. 5,006,788, issued to Goulette, et al. on Apr. 9, 1991. The Goulette patents are directed toward measuring radiating electromagnetic emissions from a circuit board, primarily for the purpose of eliminating or monitoring electromagnetic interference generated by a circuit board or the components mounted thereon. Goulette's approach is not directed toward testing a printed circuit board for manufacturing defects which do not result in interfering levels of electromagnetic radiation. There are numerous other patents, as cited in the Goulette patents, which are directed toward testing printed circuit boards for undesirable radiating emissions.
One other approach to testing for defective connections in a populated printed circuit board is described in U.S. Pat. No. 4,779,041 to Williamson, Jr. That patent describes a testing method in which two probes are connected to printed circuit board traces that are supposed to be connected to leads of an integrated circuit. If those leads are properly connected to the PC board, a current can be injected into one lead, forward biasing a parasitic diode which forms in the chip's substrate between the lead and ground. A second, larger current pulse, is then injected into the second lead. If both leads are connected to the printed circuit board, the second current flow will cause a measurable voltage drop across the inherent resistance of the substrate. Thus, a change in voltage in response to the second current pulse tends to indicate that the component is properly connected to the PC board. This technique relies on the existence of a common impedance in the path to ground from multiple leads in an integrated circuit. Such a common impedance is not always present. When such a common impedance is present, it is usually very low, and relatively high currents must be applied to the circuit to produce a measurable voltage change. Under some circumstances, such high currents can damage sensitive integrated circuit chips.
There is thus a need in the art for a device and method that will determine whether all of the leads of components mounted on a printed circuit board are properly connected (e.g., soldered) to the circuit board. There is a further need in the art for such a device that does not require generation of functional test vectors, and that does not require backdriving or otherwise isolating adjacent components on the PC board. There is a further need for a tester that does not rely on the existence of a common impedance between device leads and ground, that does not require application of undesirably high currents to integrated circuits, and that does not require the circuit board being tested to be functioning or energized while the test is being performed. There is still further need in the art for such a system that can operate with a signal to noise ratio adequate to prevent frequent false readings and that does not require precise and complex fixturing to position the sensors adjacent the board being tested. Also, there is a need for a system that can detect failures even if the components mounted on the PC board contain electromagnetic shielding or if the failure is a hairline fracture.